In many analog circuits, voltages are stored in capacitors or other charge stores. In this case, the stored voltages are often used for further signal processing. In this case, the charge stores may be formed as a switchable network of a plurality of partial charge stores.
The buffer storage of voltages for later further processing is used in analog-to-digital converters, for example. FIG. 4 shows one embodiment of an analog-to-digital converter with a pipeline architecture. The analog-to-digital converter shown for converting an analog input voltage Vs into a digital value Y comprises n cascaded stages A1, A2, . . . , An, which in each case generates a binary value B1, B2, . . . , Bn having one or more bits for the digital value Y and outputs it to a buffer BUF. In the buffer BUF, the binary values B1, B2, . . . , Bn are combined to form the digital value Y. In this case, the individual binary values B1, B2, . . . , Bn are generated temporally successively, the first stage A1 generating the binary value B1 from the voltage Vs present and outputting it to the buffer BUF. A result of the processing of the voltage signal Vs is output as voltage signal Vs2 to the second stage A2 for further processing. The voltage signal Vsn finally serves as an input signal for the last stage An.
FIG. 5 shows an exemplary embodiment of a conventional sample-and-hold device such as can be used in one of the stages A1 to An. The sample-and-hold device for processing differential input signals comprises input terminals Vinp and Vinn and also reference potential terminals Vrefp and Vrefn. The sample-and-hold device furthermore has capacitors C1, C2, which can be connected by first terminals to the input terminals Vinp, Vinn and the reference potential terminals Vrefp, Vrefn via switches S93 to S98. In this case, the switches S93 to S98 can be controlled by a control circuit CC. Second terminals of the capacitors C1, C2 are coupled to an inverting and a noninverting input of a differential amplifier OP. The noninverting output O1 of the differential amplifier OP is connected to the inverting input of the differential amplifier OP via a parallel circuit formed by a feedback capacitor CR1 and a switch S91. A parallel circuit formed by a feedback capacitor CR2 and a switch S92 is likewise connected between the inverting output O2 of the differential amplifier OP and its noninverting input.
One of the voltage signals Vs to Vsn can be fed in differential form via the input terminals Vinp, Vinn. In this case, the components of a signal at the input terminals Vinp, Vinn are complementary to one another with regard to a common mode potential. In a first phase, a sample phase, the switches S91, S92, S93, S94 are closed, while the switches S95, S96, S97, S98 are open. The capacitors C1, C2 are thereby charged in a manner corresponding to the input voltage.
In a subsequent phase, a hold phase, the switches S91, S92, S93, S94 are opened depending on a control by the control circuit. For example in a manner governed by a binary value, one of the capacitors C1, C2 is coupled to a first reference potential terminal Vrefp and the other is coupled to a second reference potential terminal Vrefn. In this case, reference potentials at the reference potential terminals Vrefp, Vrefn are usually likewise complementary to one another with regard to the reference voltage. As a result of the reference potentials being applied to the capacitors C1, C2, in a manner dependent on the switch position of the switches S95 to S98, a voltage can be added to the voltage stored in the capacitors C1, C2 or can be subtracted from the stored voltage. A result of this operation is output at the terminals O1, O2.
At the end of the hold phase, charges that are dependent on the stored voltages and the switch positions of the switches S95 to S98 are applied to the capacitors C1, C2. In a subsequent sample phase for storing new voltage values of the input voltage, the charge state of the capacitances C1, C2 can influence the sample operation. If a residual charge depends on a binary value from the analog-to-digital conversion, this may lead, particularly at high sampling rates, to so-called intersymbol interferences. Errors of this type impair the accuracy in the analog-to-digital conversion.